1. Field of the Invention
The present invention relates to a layout data conversion method in which layout data need not be amended even when the design of, for example, a standard-cell type semiconductor integrated circuit is changed. And more particularly, it relates to a semiconductor integrated circuit which uses a digital type standard cell.
2. Description of the Related Art
In designing a semiconductor integrated circuit, data which were used in designing a previous circuit are preferably utilized to increase the density of the semiconductor integrated circuit. However, if the data are simply converted, there will arise problems including deterioration in the shapes of patterns and separation of wiring or the like from a predetermined connection portion to which the wiring is supposed to be connected. Hence, major corrections must be made to the data. Under the circumstances, there is a need for a layout data conversion method in which only little correction of data is needed after data conversion.
In designing a semiconductor integrated circuit, especially at a layout designing step, logic gates are arranged and interconnected based on connection information which is created when the logic is designed and the logic cell library which is used. During the layout designing step, it is necessary to reduce the chip area as much as possible while satisfying constraints which are imposed due to fabrication conditions.
Over the past few years, as the need for larger semiconductor integrated circuits and more efficient designs has increased, a designing method which makes it possible to design a very dense circuit in a short time has been sought. To this end, designers repeatedly shift + reduce layout data which were used in designing previous semiconductor integrated circuits, in particular, the patterns of basic pattern units of the previous circuits, to thereby reduce the time which is required in designing new circuits.
The "shift" term herein refers to reduction in the size in a vertical direction or a horizontal direction during repeated use of layout data. The "reduce" term herein refers to general even reduction of data with one point of the data as the center of reduction.
FIG. 5 is a view showing an example of data conversion achieved by conventional shift. In FIG. 5, there is illustrated a case where original layout data of FIG. 5A in which patterns of basic pattern units are repeatedly used are subjected to horizontal minus shift to obtain similar repeated patterns in which the area of each basic pattern unit of a circuit is reduced, thereby obtaining layout data such as that shown in FIG. 5B. In FIG. 5A, a wiring of a basic pattern unit is shown in a rectangular shape. In this case, cells which are adjacent to each other form a pair, whereby a data set is obtained. If a minus shift is simply performed, wiring of adjacent cells which used to be in contact to each other at four positions will be separated from each other as shown in FIG. 5B, which makes it impossible to use the layout data as they are in FIG. 5B at a subsequent designing step. It then follows that the layout data of FIG. 5B must be corrected.
Manual layout or solid-merge-shift can be adopted as correction means. The former is to correct connection using a CAD tool. According to the latter approach, since left data and right data of FIG. 5A, for example, can be regarded as separate parts even through they are in contact with each other, they are treated as one horizontally long data (i.e., treated as one solid pattern), and two points in a vertical direction are selected at each end of the elongation of the pattern so that data are picked up only at these selected four points (i.e., merging). Following this, these data are subjected to minus shift. Hence, a pattern which is obtained by shift is equal to the original pattern as it is reduced in the horizontal direction, and therefore, no space is created in the center of the post-shift pattern.
The former means, requiring manual labor to perform correction, takes time. On the other hand, the latter means demands that data are partially deleted to be used as data of a long pattern, and hence, if data that are processed are taken into consideration, an increased amount of data must be used.
As such a method of converting layout data of a semiconductor integrated circuit device described above, Japanese Unexamined Patent Publication (KOKAI) No. 2-181272 published on Jul. 16, 1990, is known, for instance. However, this prior art only discloses a method of converting wiring data into loop data in the case where data about optional wiring are stored as line data in layout data. In this prior art, no consideration is taken at all as to inconvenience, due to conversion of a portion of wiring data, of the disconnections that may be created in adjacent wiring. The prior art does not disclose how to deal with such inconvenience.
Another Japanese Unexamined Patent Publication (KOKAI) No. 4-115367 published on Apr. 16, 1992, is directed to a layout pattern designing apparatus for designing an analog LSI function cell. According to the disclosed method of designing a layout pattern, data on basic cells are first prepared which have a plurality of types of circuit structures and element values. At the same time, a data changeable range is designated for each basic cell. After considering the changeable ranges of electric characteristics of an analog circuit and the configurations of elements, a basic layout pattern is generated.
Next, a basic cell which needs a change in the configuration or the element value is corrected, followed by determinationment as to violation of design rules. If it is determined that there is violation of the design rules, necessary correction is repeatedly performed until the violation of the design rules is eliminated.
Since the conventional method above is related to a layout pattern designing apparatus for designing an analog LSI function cell, a number of wiring parts and element parts are used and the interconnections between these parts are complex. Hence, even a partial change in the wiring parts and the element parts influences many other parts. This makes it necessary to change many other parts, consequently degrading design efficiency. In addition, since the basic cells are changed one at a time, the changes become complicated, which then take an enormously long time to implement.
Further, in the conventional art above, since the basic cells are treated simply in a plane, it is necessary to define various conditions of the changeable range for each basic cell. Hence, computation becomes complex and takes a long time.